1. Field of the Invention
The present invention relates to integrated circuits, and, in particular, to software tools used to program field programmable gate arrays (FPGAs) and other programmable logic devices.
2. Description of the Related Art
FIG. 1 shows a simplified schematic block diagram of a conventional FPGA 100 comprising a (2xc3x972) array of programmable blocks. Each block in FPGA 100 comprises a programmable function unit (PFU) 102 and a supplemental logic and interconnect cell (SLIC) 104. Connected to these blocks are input/output (I/O) blocks. Each I/O block comprises four programmable I/O units (PIOs) connected to a programmable switch box. For example, four PIOs 106 are connected to programmable switch box 108, and four PIOs 110 are connected to programmable switch box 112. In addition, FPGA 100 is configured with horizontal and vertical wiring that provide routing resources for connecting the various functional elements (e.g., PIOs, PFUs, and SLICs) within the FPGA. For example, switch box 108 is configured to be programmed to enable PIOs 106 to drive certain vertical wires 114, while switch box 112 is configured to be programmed to enable PIOs 110 to drive certain horizontal wires 116. In addition to switch boxes, such as switch boxes 108 and 112, which provide programmable interconnects between two different sets of wires, FPGA 100 also has programmable placed switches 118, each of which enables a corresponding pair of intersecting horizontal and vertical wires to be connected (e.g., vertical wires 114 and horizontal PFU wires 120 or horizontal wires 116 and vertical PFU wires 122). FPGA 100 will typically include much more routing resources to, from, and between the various functional elements than that shown in FIG. 1, as well as additional programmable switches and other logic components.
In general, an FPGA is a particular type of a programmable logic device (PLD) that can be programmed by the user for any of a wide range of specific applications. In theory, an FPGA, such as FPGA 100 of FIG. 1, is provided with routing resources to connect (i.e., route) any pin on any component (e.g., a PFU, SLIC, or PIO) within the FPGA to any other pin on any other component within the FPGA. These connections are made by programming one or more programmable switches in the FPGA to establish a contiguous wiring path between the two pins. For example, in FIG. 1, PIO 106-1 can be connected to pin 2 of PFU 102 by (i) programming switch box 108 to connect PIO 106-1 to vertical wire 114 and (ii) programming placed switch 118 to connect vertical wire 114 to horizontal wire 120, which is hard-wired to pin 2 of PFU 102.
Special software tools have been developed for programming FPGAs. One such programming tool is the Epic(trademark) program provided to customers of FPGAs sold by Agere Systems Inc. of Berkeley Heights, N.J. Programming tools like the Epic(trademark) program can be used by a programmer to generate graphical displays showing representations of the current programming of the FPGA. Although these graphical representations may conform generally to the actually physical design and layout of the physical FPGA chip, in fact, they are merely representations of the functionality provided by the FPGA. As such, the appearance of functional elements and routing resources in the graphical displays generated by the programming tool need not correspond identically to those in the actual FPGA device.
In conventional software tools for programming FPGAs, different types of switches are typically supported. As described previously in the context of FIG. 1, an FPGA may have both programmable switch boxes, such as switch boxes 108 and 112 as well as programmable placed switches, such as placed switches 118.
FIG. 2 shows a schematic representation of a placed switch 200, similar to placed switch 118 of FIG. 1. Placed switch 200 can be programmed to connect horizontal wire 202 with xe2x80x9cintersectingxe2x80x9d vertical wire 204. When placed switch 200 is on, it provides a connection between wires 202 and 204, and, when placed switch 200 is off, it does not provide such a connection. In conventional programming tools for FPGAs, in order for a horizontal wire to be connected to a vertical wire by a placed switch, the two wires must intersect one another in the graphical display of the FPGA generated by the programming tool.
FIG. 3 shows a schematic representation of a switch box 300, similar to switch boxes 108 and 112 of FIG. 1. In theory, switch box 300 can be implemented to programmably connect independently any of input wires 302 to any of output wires 304. If the two input wires 302 are labeled A and B and the two output wires 304 are labeled C and D, switch box 300 can be programmed in any of the sixteen different combinations of connections listed in Table I. In conventional programming tools for FPGAs, in order for an input wire to be connected to an output wire by a switch box, the two wires must be connected to the switch box in the graphical display of the FPGA generated by the programming tool.
FIG. 4 shows a schematic representation of a pseudo arc, another type of switch connection. A pseudo arc is the connection provided from an input wire 402 to an output wire 404 through a logic element 400, such as a PFU or a SLIC. Typically, a pseudo arc is a conditional switch connection that depends on the logic implemented within element 400. In conventional programming tools for FPGAs, in order for an input wire to be connected to an output wire via a pseudo arc, the two wires must be connected to the same logic element in the graphical display of the FPGA generated by the programming tool.
FIG. 5 shows an example of a graphical display generated by the Epic(trademark) program for a particular FPGA. FIG. 5 shows a display representing the entire FPGA in a single view. For a typical application, an FPGA such as that shown in FIG. 5 will be programmed with a large number of connections between the various functional elements. In order to be useful to programmers, the Epic(trademark) program enables a programmer to generate displays that selectively reveal individual wiring routes between particular functional elements, including the programming of the individual switches that provide those routes. In addition, the Epic(trademark) program can display all possible connections from a selected switch-box pin. The Epic(trademark) program also enables a programmer to zoom in on any selected region of the display.
FIG. 6 shows an example of a graphical display of one particular region of the FPGA shown in FIG. 5. In particular, FIG. 6 shows a switch box 600 having a number of input pins 602 and a number of output pins 604. In the display of FIG. 6, no connections are shown between any of the input and output pins.
FIG. 7 shows an example of a graphical display of switch box 600 of FIG. 6 displaying all of the possible switch-box connections 702 involving a particular input pin 602. As shown in FIG. 7, switch box 600 can be independently programmed to provide a different switch-box connection 702 from input pin 602 to each different output pin 604.
FIG. 8 shows an example of a graphical display of an entire route from output pin 804 of PFU 802 to input pin 810 of SLIC 812. In particular, the entire route consists of (1) wire 806 connecting output pin 804 to input pin 602 of switch box 600, (2) switch-box connection 702 connecting input pin 602 to output pin 604 of switch box 600, and (3) wire 808 connecting output pin 604 to input pin 810 of SLIC 812.
In order for an FPGA to be programmed with a particular route, two requirements must be satisfied: (1) the set of actual connections that provide the particular route must be able to be made in the actual FPGA and (2) the set of actual connections that provide the particular route must be able to be represented in the graphical displays generated by the programming tool used to program the actual FPGA. Since the programming tool relies on a representation of the actual FPGA configuration, being able to satisfy the first requirement does not necessarily mean that the second requirement will also be able to be satisfied.
In general, the types of connections (e.g., switch boxes, placed switches, and pseudo arcs) that are supported by conventional programming tools for FPGAs, such as the Epic(trademark) program, have imposed constraints on the architectures of the actual FPGAs, because certain connections that could in theory be supported in actual FPGAs could not be represented using the types of connections supported by the conventional programming tools. For example, the types of connections supported by conventional programming tools require two wires to be co-located in the display generated by the programming tool in order for those wires to be connected. This means that the two wires have to either intersect one another or terminate at the same functional element. As a result, the number of different pins that could be designed into a particular functional element in the actual FPGA was limited by the number of corresponding wires connected to those pins that could be effectively represented in the graphical displays generated by the programming tool. As such, there was no point in designing FPGAs with functional elements having more than this number of pins, since such FPGAs could not be efficiently or reliably programmed using conventional programming tools. As such, FPGAs have not been designed with such architectures.
The present invention is directed to a software tool for programming an FPGA that provides a novel technique for representing connections within an FPGA. In particular, in addition to all of the conventional placed switches, switch boxes, and pseudo arcs, embodiments of the present invention are able to represent FPGA connections using hidden switches. A hidden-switch connection is a connection between two functional elements that is represented in the graphical display generated by an FPGA programming software tool without explicitly representing the one or more switch devices that would provide the corresponding connection in the actual FPGA. In particular, a hidden-switch connection is represented in the graphical display as a curve (e.g., a diagonal straight line) from a jumper wire on one functional element to another jumper wire on another functional element, where a jumper wire is represented in the graphical display as a wire connected at one end to a pin of the corresponding functional element and unconnected at the other end.
In one embodiment, the present invention is a method for representing programming for a programmable logic device (PLD), comprising the steps of (a) storing a software representation of the PLD; and (b) generating, based on the software representation of the PLD, a graphical display representing a hidden-switch connection between first and second functional elements in the PLD, wherein, in the graphical display, the hidden-switch connection is represented by a curve from a first jumper wire at a pin of the first functional element to a second jumper wire at a pin of the second functional element, wherein each jumper wire is represented as being connected to the corresponding pin of the corresponding functional element at a first end of the jumper wire and unconnected at a second end of the jumper wire.